The present invention relates to the design of integrated circuits (ICs), and more specifically, to a method, system and computer program product that provides for improved localized self-heating analysis during IC design primarily at the gate level.
In the normal operation of ICs, it is known that the switching of transistors designed into the IC consumes electrical power, which generates heat that causes a rise in the temperature at various locations (“hot spots”) within the IC. This is commonly known as self-heating or DeltaT (i.e., temperature change).
Transistors are one of the basic building blocks of design elements or cells (e.g., an inverter, a NAND gate, a latch, etc.) within a typical IC. A single cell may comprise a relatively large number of transistors and other building blocks (e.g., resistors, capacitors, etc.), depending on the specific functionality of that type of cell. A designer of an IC typically may have a library of hundreds or even a thousand or more cells from which to choose when designing the various macro functions of a particular IC.
The increased temperature of the IC at certain locations may impact and/or cause, for example, leakage currents, circuit delays, circuit functionality, and both front end of the line (FEOL) and back end of the line (BEOL) IC fabrication reliability. Thus, it is desirable when designing an IC to perform an analysis of the progressing IC design to accurately identify localized hot spots in the design and revise the IC design to correct for these hot spots (i.e., to better dissipate the heat through the various devices formed in the IC along with the wires and substrate).
What is needed is an improved method for analysis of localized self-heating within an IC during the gate design phase, wherein the analysis accurately captures the heterogeneity of the self-heating or DeltaT within a cell of the IC in a relatively rapid and efficient “in-context” manner and relatively early in the IC gate level design flow process.